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FEDL63193-04
1 Semiconductor ML63193
GENERAL DESCRIPTION
This version: Sep. 2001 Previous version: Mar. 2000
4-Bit Microcontroller with Built-in 1024-Dot Matrix LCD Driver and Melody Circuit.
The ML63193 is CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers (64 SEG. x 16 COM.), and operates at 0.9 V (Min). The ML63193 is suitable for applications as games, toys, watches, remote controller, etc. Which are provided with a LCD display. The ML63193 is an M6318x series mask ROM-version product of OLMS-63K family, which employs Oki's original CPU core nX-4/250.
FEATURES
* Extensive instruction set 408 instructions: Transfer, rotate, increment/decrement, arithmetic operations, compare, logic operations, mask operations, bit operations, ROM table reference, stack operations, flag operations, jump, conditional branch, call/return, control * Wide variety of addressing modes Indirect addressing mode for 4 types of data memory with current bank register, extra bank register, HL register and XY register Data memory bank internal direct addressing mode * Processing speed 2 clocks per machine cycle, with most instructions executed in 1 machine cycle Minimum instruction execution time : 61 s (@ 32.768 kHz system clock) : 1 s (@ 2 MHz system clock) * Clock generation circuit Low-speed clock High-speed clock : Crystal oscillation or RC oscillation selected with mask option (30 kHz to 80 kHz) : Ceramic oscillation or RC oscillation selected with software (2 MHz max)
* Program memory space 64 K words Basic instruction length is 16 bits/1word. * Data memory space 2048 nibbles * Stack level Call stack level Register stack level
: 16 levels : 16 levels
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* I/O Ports Input ports: Selectable as input pull-up resistor/input pull-down resistor/high impedance input. I/O ports: Selectable as input pull-up resistor/input pull-down resistor/high impedance input. Selectable as P-channel open drain output/N-channel open drain output/high-impedance output/ CMOS output. Can be interfaced with external peripherals that use a different power supply than this device uses.VDDI is the power supply pin for ports. Number of ports: Input port : 1 port x 4 bits Input-output port : 5 ports x 4 bits * Melody output Melody frequency Tone length Tempo Melody data Buzzer driver signal output * LCD driver Number of segments Duty Bias Frame frequency Contrast Display modes
: 529 Hz to 2979 Hz : 63 varieties : 15 varieties : Stored in program memory : 4 kHz
: : : :
1024 Max. (64 SEG. x 16 COM.) Selectable as 1/1 to 1/16 duty Selectable as 1/4 or 1/5 bias (regulator built-in) ex. 64 Hz (at 1/16 duty), 128 Hz (at 1/8 duty), 256 Hz (at 1/4 duty), 512 Hz (at 1/2 duty), 1024 Hz (at 1/1 duty) : 16 levels adjustable : Selectable as all-ON mode/all-OFF mode/power down mode/ normal display mode : (8 bits)x(8 bits) Product (16 bits) : (16 bits)/(8 bits) Quotient (16 bits), Remainder (8 bits)
* Multiplier/divider circuit Multiplier Divider
* System reset function System reset through RESET pin (selectable as built-in 2 kHz RESET-Sampling circuit by mask option) System reset by power-on detection (When not using 2 kHz RESET-Sampling circuit) System reset by low-speed oscillation halt * Battery check Low-voltage supply check The value of the judgment voltage is selected by the software (by setting the LD1 and LD0 bits of BLDCON).
LD1 0 0 1 1 LD0 0 1 0 1 Judgment Voltage (V) 1.05 0.10 1.20 0.10 1.80 0.10 2.40 0.10 Remarks Ta = 25C Ta = 25C Ta = 25C Ta = 25C
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* Timers and Counter 8-bit timer
Watchdog timer 100 Hz timer 15-bit time-base counter
:4 Selectable as auto-reload mode/capture mode/ clock frequency measurement mode :1 :1 Measurable in steps of 1/100 sec. :1 1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
* Serial port Mode : Selectable as UART mode, synchronous mode UART communication speed : 1200 bps, 2400 bps, 4800 bps, 9600 bps Clock frequency in synchronous mode : Internal clock mode (32.768 kHz), External clock frequency Data length : 5 to 8 bits * Shift register Shift clock Data length * Interrupt factors External interrupt Internal interrupt * Operating temperature : 1x or 1/2 x system clock, timer 1 overflow, external clock : 8 bits
:4 : 14 (watchdog timer interrupt is a nonmaskable interrupt) : -20 to +70 C
* Power supply backup Backup circuit (voltage multiplier) enables operation at 0.9 V minimum. * Power supply voltage When backup used
When backup not used
: 0.9 V to 2.7 V (Operating frequency: 30 k to 80 kHz) 1.2 V to 2.7 V (Operating frequency: 300 k to 500 kHz) 1.5 V to 2.7 V (Operating frequency: 200 k to 1 MHz) : 1.8 V to 5.5 V (Operating frequency: 200 k to 2 MHz)
* Package: Chip (128 pads) : (Product name: ML63193-XXXWA) 144-pin plastic LQFP (LQFP144-P-2020-0.50-K) : (Product name: ML63193-xxxTC) xxx indicates a code number.
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MASK OPTION
In the ML63193 uses the mask option to specify the following functions: * Low-Speeed clock oscillation circuit Specify the crystal oscillation circuit or the RC oscillation circuit for the low-speed clock oscillation circuit. * Reset signal sampling Specify whether or not the reset signal will be sampled at 2 kHz. When specifying "will carry out 2 kHz sampling," hold the RESET pin at a "H" level for 1 ms or more. To use the mask option, assign mask option data in the application program in accordance with the formats below. The mask option area is an application program execution disabled area. Mask Option Data Assignment Format
Function Low-speed clock oscillation circuit (crystal oscillation circuit/RC oscillation circuit) Reset signal sampling (will/will not carry out 2 kHz sampling) 0FFE0H bit 1 Mask option area bit bit 0 data 0 1 0 1 Option to be selected Crystal oscillation circuit RC oscillation circuit Will carry out 2 kHz sampling Will not carry out 2 kHz sampling
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BLOCK DIAGRAM
Asterisks (*) indicate the secondary function of each port. Signal names enclosed by chain lines ( Indicate interface signals of the VDDI power supply system. )
CPU core nX-4/250 TIMING CONTROL SP RSP STACK CAL.S:16-level REG.S:16-level ALU MIE INSTRUCTION DECODER IR INT 4 RAM 2048N INT 2 SIO INT193 INT 1 SFT RESET TST1 TST2 RST INT DATA BUS TST 4 TBC MULDIV INT 1 MELODY CBR EBR H X L Y C RA A G Z BUS CONTROL PC ROM 64KW
TIMER 8bit (4ch)
TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK* RXC* TXC* RXD* TXD* SCLK* SIN* SOUT* MD MDB
XT0 XT1 OSC0 OSC1 VDDH VDD CB1 CB2 VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDL OSC INT 1 INT 1 BACK UP
BLD
INT 1
INPUT PORT
P0.0 - P0.3
100HzTC P9.0 - P9.3 WDT INT 3 PA.0 - PA.3 I/O PORT PB.0 - PB.3 PC.0 - PC.3 PE.0 - PE.3
BIAS
LCD & DSPR
COM1 - 16 SEG0 - 63 VDDI VSS
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PIN CONFIGURATION (TOP VIEW)
(NC) (NC) SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 (NC) (NC)
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
(NC) SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS P0.3 P0.2 P0.1 P0.0 P9.3 P9.2 P9.1 P9.0 PA.3 PA.2 PA.1 PA.0 PB.3 PB.2 PB.1 PB.0 (NC) (NC)
(NC) (NC) (NC) PC.3 PC.2 PC.1 PC.0 PE.3 PE.2 PE.1 PE.0 VDDI MDB MD TST2 TST1 XT0 XT1 RESET OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS (NC) (NC)
Note: Pins marked as (NC) are no-connection pins which are left open.
(NC) (NC) SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG49 SEG48 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 (NC) (NC)
144-Pin Plastic LQFP (TC: LQFP144-P-2020-0.50-K)
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PAD CONFIGURATION
Pad Layout PC.3 PC.2 PC.1 PC.0 PE.3 PE.2 PE.1 PE.0 VDDI MDB MD TST2 TST1 XT0 XT1 RESET OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PB.0 96 PB.1 97 PB.2 98 PB.3 99 PA.0 100 PA.1 101 PA.2 102 PA.3 103 P9.0 104 P9.1 105 P9.2 106 P9.3 107 P0.0 108 P0.1 109 P0.2 110 P0.3 111 VSS 112 COM1 113 COM2 114 COM3 115 COM4 116 COM5 117 COM6 118 COM7 119 COM8 120 SEG0 121 SEG1 122 SEG2 123 SEG3 124 SEG4 125 SEG5 126 SEG6 127 SEG7 128
ML63193
Y
(0,0)
X
COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40
Note: The chip substrate voltage is VSS.
SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 Chip size Chip thickness Coordinate origin Pad hole size Pad size Minimum pad pitch : 5.72 mm x 5.72 mm : 350 m (280 m: available as required) : center of chip : 100 m x 100 m : 110 m x 110 m : 140 m
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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Pad Coordinates
Center of chip: X = 0, Y = 0 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Pad Name SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 X (m) -2204 -2063 -1923 -1783 -1642 -1502 -1361 -1221 -1081 -940 -800 -659 -519 -379 -238 -98 43 183 323 464 604 745 885 1025 1166 1306 1447 1587 1727 1868 2008 2149 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 Y (m) -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2149 -2008 -1868 -1727 -1587 -1447 -1306 -1166 -1025 -885 -745 Pad No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Pad Name SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 VSS VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDH CB1 CB2 VDD VDDL OSC1 OSC0 RESET XT1 XT0 TST1 TST2 MD MDB X (m) 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2152 2011 1871 1730 1590 1450 1309 1169 1028 888 748 607 467 326 186 46 -95 -235 -376 -516 -656 -797 Y (m) -604 -464 -323 -183 -43 98 238 379 519 659 800 940 1081 1221 1361 1502 1642 1783 1923 2063 2204 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714 2714
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Center of chip: X = 0, Y = 0 Pad No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 Pad Name VDDI PE.0 PE.1 PE.2 PE.3 PC.0 PC.1 PC.2 PC.3 PB.0 PB.1 PB.2 PB.3 PA.0 PA.1 PA.2 PA.3 P9.0 P9.1 P9.2 P9.3 X (m) -937 -1078 -1218 -1358 -1499 -1639 -1780 -1920 -2060 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 Y (m) 2714 2714 2714 2714 2714 2714 2714 2714 2714 2246 2106 1966 1825 1685 1544 1404 1264 1123 983 842 702 Pad No. 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Pad Name P0.0 P0.1 P0.2 P0.3 VSS COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 X (m) -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 -2714 Y (m) 562 421 281 140 0 -140 -281 -421 -562 -702 -842 -983 -1123 -1264 -1404 -1544 -1685 -1825 -1966 -2106 -2246
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PIN DESCRIPTIONS
The basic functions of each pin of the ML63193 are described in Table 1. A symbol with a slash "/" denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For type, "--" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an input-output pin. Table 1 Pin Descriptions (Basic Functions)
Function Symbol VDD VSS VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 Power Supply VDDI Pin No. 50 39,91 40 41 42 43 44 45 46 61 Pad No. 76 65,112 66 67 68 69 70 71 -- 72 87 -- Capacitor connection pins for LCD bias generation: A capacitor (0.1 F) should be connected between C1 and C2. Positive power supply pin for external interface (Power supply for input, and input-output ports) Positive power supply pin for internal logic (internally generated): A capacitor (0.1 F) should be connected between this pin and VSS. Voltage multiplier pin for power supply backup (internally generated): A capacitor (1.0 F) should be connected between this pin and VSS. Pins to connect a capacitor for voltage multiplier. -- CB2 49 75 A capacitor (1.0 F) should be connected between CB1 and CB2. Low-speed clock oscillation pins: An option for using crystal oscillation or RC oscillation is chosen by the mask option. If the crystal oscillation is chosen, a crystal should be connected between XT0 and XT1, and capacitor (CG) should be connected between XT0 and VSS. If the RC oscillation is chosen, external oscillation resistor (ROSL) should be connected between XT0 and XT1. High-speed clock oscillation pins: A ceramic resonator and capacitors (CL0, CL1) or external oscillation resistor (ROSH) should be connected to these pins. -- Type -- -- Description Positive power supply pin Negative power supply pin Power supply pins for LCD bias (internally generated): Capacitors (0.1 F) should be connected between these pins and VSS.
VDDL
51
77
--
VDDH
47
73
--
CB1
48
74
XT0
56
82
I
Oscillation
XT1
55
81
O
OSC0 OSC1
53 52
79 78
I O
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Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol TST1 Test TST2 58 84 I Pin No. 57 Pad No. 83 Type I Description Input pins for testing. A pull-down resistor is internally connected to these pins. The user cannot use these pins. System reset input pin. Setting this pin to "H" level puts this device into a reset state. Then, setting this pin to " L" level starts executing an instruction from address 0000H. Reset RESET 54 80 I An option for using RESET sampling circuit or not using is chosen by the mask option. When using RESET sampling circuit, the system reset mode is entered by holding the RESET pin at a " H" level for 1ms or more. A pull-down resistor is internally connected to this pin. Melody MD MDB 59 60 85 86 O O Melody output pin (non-inverted output) Melody output pin (inverted output)
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Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol P0.0/INT5 P0.1/INT5 P0.2/INT5 P0.3/INT5 P9.0 P9.1 P9.2 P9.3 PA.0 PA.1 PA.2 PA.3 PB.0/INT0/ TM0CAP/ TM0OVF Port PB.1/INT0/ TM1CAP/ TM1OVF PB.2/INT0/ T02CK PB.3/INT0/ T13CK PC.0/INT1/ RXD PC.1/INT1/ TXC PC.2/INT1/ RXC PC.3/INT1/ TXD PE.0/SIN PE.1/SOUT PE.2/SCLK PE.3/INT2 Pin No. 87 88 89 90 83 84 85 86 79 80 81 82 75 Pad No. 108 109 110 111 104 105 106 107 100 101 102 103 96 I/O I/O 4-bit input output ports: In input mode, pull-up resister input, pull-down resister input, or high-impedance input is selectable for each bit. In output mode, P-channel open drain output, Nchannel open drain output, CMOS output, or highimpedance output is selectable for each bit. I Type Description 4-bit input port: Pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit.
76
97
I/O
77 78 66 67 68 69 62 63 64 65
98 99 92 93 I/O 94 95 88 89 90 91 I/O
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Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 LCD SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 Pin No. 92 93 94 95 96 97 98 99 27 28 29 30 31 32 33 34 100 101 102 103 104 105 106 107 111 112 113 114 115 116 117 118 119 Pad No. 113 114 115 116 117 118 119 120 57 58 59 60 61 62 63 64 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 O LCD segment signal output pins O Type Description LCD common signal output pins
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Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 LCD SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 Pin No. 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 3 4 5 6 7 8 9 10 11 12 Pad No. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 O Type Description LCD segment signal output pins
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Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 LCD SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 Pin No. 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pad No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 O Type Description LCD segment signal output pins
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Table 2 shows the secondary functions of each pin of the ML63193. Table 2 Pin Descriptions (Secondary Functions)
Function Symbol PB.0/INT0 PB.1/INT0 PB.2/INT0 PB.3/INT0 PC.0/INT1 PC.1/INT1 External Interrupt PC.2/INT1 PC.3/INT1 PE.3/INT2 P0.0/INT5 P0.1/INT5 P0.2/INT5 P0.3/INT5 PB.0/ TM0CAP PB.1/ TM1CAP PB.0/ TM0OVF Timer PB.1/ TM1OVF PB.2/T02CK PB.3/T13CK Pin No. 75 76 77 78 66 67 68 69 65 87 88 89 90 75 76 75 76 77 78 Pad No. 96 97 98 99 92 93 94 95 91 108 109 110 111 96 97 96 97 98 99 I I O O I I I I I I Type Description External 0 interrupt input pins The change of input signal level causes an interrupt to occur. The Port B Interrupt Enable register (PBIE) enables or disables an interrupt for each bit. External 1 interrupt input pins The change of input signal level causes an interrupt to occur. The Port C Interrupt Enable register (PCIE) enables or disables an interrupt for each bit. External 2 interrupt input pin The change of input signal level causes an interrupt to occur. External 5 interrupt input pins The change of input signal level causes an interrupt to occur. The Port 0 Interrupt Enable register (P0IE) enables or disables an interrupt for each bit. Timer 0 capture input pin Timer 1 capture input pin Timer 0 overflow flag output pin Timer 1 overflow flag output pin External clock input pin for timer 0 and timer 2. External clock input pin for timer 1 and timer 3
Capture
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Table 2 Pin Descriptions (Secondary Functions) (continued)
Function Symbol PC.0/RXD Pin No. 66 Pad No. 92 Type I Description Serial port receive data input pin Sync serial port clock input-output pin Transmit clock output when this device is used as a master processor. Transmit clock input when this device is used as a slave processor. Sync serial port clock input-output pin Receive clock output when this device is used as a master processor. Receive clock input when this device is used as a slave processor. Serial port transmit data output pin Shift register receive data input pin Shift register transmit data output pin Shift register clock input-output pin. Clock output when this device is used as a master processor. Clock input when this device is used as a slave processor.
PC.1/TXC
67
93
I/O
Serial Port
PC.2/RXC
68
94
I/O
PC.3/TXD PE.0/SIN PE.1/SOUT Shift Register PE.2/SCLK
69 62 63
95 88 89
O I O
64
90
I/O
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ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Power supply voltage 1 Power supply voltage 2 Power supply voltage 3 Power supply voltage 4 Power supply voltage 5 Power supply voltage 6 Power supply voltage 7 Power supply voltage 8 Input voltage 1 Input voltage 2 Output voltage 1 Output voltage 2 Output voltage 3 Output voltage 4 Output voltage 5 Output voltage 6 Output voltage 7 Output voltage 8 Storage temperature Symbol VDD1 VDD2 VDD3 VDD4 VDD5 VDD VDDI VDDH VIN1 VIN2 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 TSTG Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C VDD input, Ta = 25C VDDI input, Ta = 25C VDD1 output, Ta = 25C VDD2 output, Ta = 25C VDD3 output, Ta = 25C VDD4 output, Ta = 25C VDD5 output, Ta = 25C VDD output, Ta = 25C VDDI output, Ta = 25C VDDH output, Ta = 25C
--
Rating -0.3 to +1.6 -0.3 to +2.9 -0.3 to +4.2 -0.3 to +5.5 -0.3 to +6.8 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to VDD + 0.3 -0.3 to VDDI + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD2 + 0.3 -0.3 to VDD3 + 0.3 -0.3 to VDD4 + 0.3 -0.3 to VDD5 + 0.3 -0.3 to VDD + 0.3 -0.3 to VDDI + 0.3 -0.3 to VDDH + 0.3 -55 to +150
Unit V V V V V V V V V V V V V V V V V V C
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RECOMMENDED OPERATING CONDITIONS
* When backup is used
(VSS = 0 V) Parameter Operating Temperature Operating Voltage Crystal Oscillation Frequency Low-speed RC Oscillation Frequency Symbol Top VDD VDDI fXT Condition
-- -- --
Rating -20 to +70 0.9 to 2.7 0.9 to 5.5 32.768 to 76.8 36 30% 33 30% 30 30% Not applied 300 k to 500 k 200 k to 1 M Not applied 200 k 30% 700 k 30% 1 M 30%
Unit C V V kHz
CG = 5 to 25 pF ROSL = 1.0 M
fROSL
ROSL = 1.1 M ROSL = 1.2 M VDD = 0.9 to 1.2 V
kHz
Ceramic Oscillation Frequency
fCM
VDD = 1.2 to 2.7 V VDD = 1.5 to 2.7 V VDD = 0.9 to 1.2 V
Hz
High-speed RC Oscillation Frequency
fROSH
ROSH = 400 k VDD = 1.2 to 2.7 V ROSH = 100 k ROSH = 75 k
Hz
* When backup is not used
(VSS = 0 V) Parameter Operating Temperature Operating Voltage Crystal Oscillation Frequency Low-speed RC Oscillation Frequency Ceramic Oscillation Frequency Symbol Top VDD VDDI fXT Condition
-- -- --
Rating -20 to +70 1.8 to 5.5 1.8 to 5.5 32.768 to 76.8 36 30% 33 30% 30 30% 200 k to 2 M 700 k 30% 1 M 30% 1.35 M 30% 2 M 30%
Unit C V V kHz
CG = 5 to 25 pF ROSL = 1.0 M
fROSL
ROSL = 1.1 M ROSL = 1.2 M
kHz
fCM
VDD = 1.8 to 5.5 V ROSH = 100 k
Hz
High-speed RC Oscillation Frequency
fROSH
VDD = 1.8 to 3.6 V
ROSH = 75 k ROSH = 51 k
Hz
VDD = 1.8 to 3.5 V, ROSH = 30 k
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* Typical characteristics of low-speed RC oscillation When backup is used/backup is not used (VDD = VDDI = 1.5 V/VDD = VDDI = 3.0 V)
Reference data 1000 fROSL [kHz] 100 10 100
1000
ROSL [k]
10000
* Typical characteristics of high-speed RC oscillation When backup is used (VDD = VDDI = 1.5 V)
Reference data 10000 fROSH [kHz] 1000 100 10
100 ROSH [k]
1000
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FEDL63193-04
Semiconductor 1
ML63193
* Typical characteristics of high-speed RC oscillation When backup is not used (VDD = VDDI = 3.0 V)
Reference data 10000 fROSH [kHz] 1000 100 10
100 ROSH [k]
1000
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FEDL63193-04
Semiconductor 1
ML63193
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) Parameter Symbol Condition 1/5 bias, 1/4 bias (Ta = 25C) -- 1/5 bias, 1/4 bias 1/5 bias VDD3 Voltage VDD3 1/4 bias (connect VDD3 and VDD2) 1/5 bias 1/4 bias 1/5 bias 1/4 bias High-speed clock oscillation stopped VDDH Voltage (Backup used) VDDH VDD = 1.5 V High-speed clock oscillation (Ceramic oscillation, 1 MHz) VDD = 1.5 V High-speed clock oscillation stopped VDDL Voltage VDDL High-speed clock oscillation (Ceramic oscillation, 1 MHz) VDD = 1.2 to 5.5 V 1.2 -- 5.5 2.0 -- 2.7 Min. Typ. Max. Unit Measuring Circuit
VDD2 Voltage VDD2 Voltage Temperature Deviation VDD1 Voltage
VDD2 VDD2 VDD1
1.7
1.8
1.9
V mV/ C
-- Typ.-0.1 Typ.-0.3 Typ.-0.2 Typ.-0.4 Typ.-0.3 Typ.-0.5 Typ.-0.4 2.8
-4.0 1/2 x VDD2 2/3 x VDD2 VDD2 2 x VDD2 3/2 x VDD2 5/2 x VDD2 2 x VDD2 --
-- Typ.+0.1 Typ.+0.3 Typ.+0.2 Typ.+0.4 Typ.+0.3 Typ.+0.5 Typ.+0.4 3.0
VDD4 Voltage VDD5 Voltage
VDD4 VDD5
1
V
1.0
1.5
2.0
Note:
1. "VDD2" changes in the range from 1.8 to 2.4 V according to the valve of Display Contrast register (DSPCNT)
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FEDL63193-04
Semiconductor 1
ML63193
DC Characteristics (2)
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) Parameter Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage Crystal Oscillation Stop Detect Time External RC Oscillator Capacitance Internal RC Oscillator Capacitance External Ceramic Oscillator Capacitance Internal RC Oscillator Capacitance POR Voltage Non-POR Voltage Symbol Condition Oscillation start time: within 5 seconds Backup used Backup not used -- Min. Typ. Max. Unit Measuring Circuit
VSTA VHOLD TSTOP
1.2 0.9 1.7 0.1
-- -- -- --
-- -- -- 5.0 ms V
CG
--
5
--
25
CD
-- CSA2.00 MG (Murata MFG.-make) used VDD = 3.0 V -- VDD = 1.5 V VDD = 3.0 V VDD = 1.5 V VDD = 3.0 V LD1 = 1, LD0 = 1, Ta = 25C LD1 = 1, LD0 = 0, Ta = 25C LD1 = 0, LD0 = 1, Ta = 25C LD1 = 0, LD0 = 0, Ta = 25C VBLDC = 2.40 V (LD1 = 1, LD0 = 1)
20
25
30 pF
CL0, CL1
--
30
-- 1
COS
8 0 0 1.2 2 2.30 1.70 1.10 0.95 -- -- -- --
12 -- -- -- -- 2.40 1.80 1.20 1.05 -3.5 -2.3 -1.6 -1.2
16 0.4 0.7 1.5 3 2.50 1.90 1.30 1.15 -- -- -- -- mV/ C V
VPOR1 VPOR2
BLD Judgment Voltage
VBLDC
BLD Judgment Voltage Temperature Deviation
VBLDC
VBLDC = 1.80 V (LD1 = 1, LD0 = 0) VBLDC = 1.20 V (LD1 = 0, LD0 = 1) VBLDC = 1.05 V (LD1 = 0, LD0 = 0)
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs. 2. "POR" denotes Power On Reset. (When not using RESET sampling circuit) 3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises up to VDD. 4. "VPOR2" indicates that POR dose not occur when VDD falls from VDD VPOR2 and again rises up to VDD.
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FEDL63193-04
Semiconductor 1
ML63193
DC Characteristics (3) * When backup is used
(Low-speed clock = Crystal oscillation (32.768 kHz), VDD = VDDI = 1.5 V, VSS = 0 V, Display contrast register (DSPCNT) = 0H, Ta = -20 to +70C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measuring Circuit
Supply Current 1
IDD1
CPU is in HALT state. (High-speed clock oscillation stopped) CPU is in HALT state. LCD is in Power Down mode. (High-speed clock oscillation stopped) CPU is in operation at low-speed oscillation. (High-speed clock oscillation stopped)
Ta = -20 to +50C Ta = -20 to +70C Ta = -20 to +50C
-- -- --
5.6 5.6 4.5
6.5 15.0 5.0
Supply Current 2
IDD2
Ta = -20 to +70C
--
4.5
13.0 A
Ta = -20 to +50C
--
23
26
1
Supply Current 3
IDD3
Ta = -20 to +70C
--
23
30
Supply Current 4 Supply Current 5
IDD4
CPU is in operation at high-speed oscillation. (approx. 700 kHz RC oscillation, ROSH = 100 k) CPU is in operation at high-speed oscillation. (1 MHz Ceramic oscillation)
--
1100
1500
IDD5
--
950
1200
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FEDL63193-04
Semiconductor 1
ML63193
DC Characteristics (4) * When backup is not used
(Low-speed clock = Crystal oscillation (32.768 kHz), VDD = VDDI = 3.0 V, VSS = 0 V, Display contrast register (DSPCNT) = 0H, Ta = -20 to +70C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Measuring Circuit
Supply Current 1
IDD1
CPU is in HALT state. (High-speed clock oscillation stopped) CPU is in HALT state. LCD is in Power Down mode. (High-speed clock oscillation stopped) CPU is in operation at low-speed oscillation. (High-speed clock oscillation stopped)
Ta = -20 to +50C Ta = -20 to +70C Ta = -20 to +50C
-- -- --
2.6 2.6 2.0
3.5 7.0 2.8
Supply Current 2
IDD2
Ta = -20 to +70C
--
2.0
6.0 A
Ta = -20 to +50C
--
12
13
1
Supply Current 3
IDD3
Ta = -20 to +70C
--
12
16
Supply Current 4 Supply Current 5
IDD4
CPU is in operation at high-speed oscillation. (approx. 700 kHz RC oscillation, ROSH = 100 k) CPU is in operation at high-speed oscillation. (2 MHz Ceramic oscillation)
--
1000
1200
IDD5
--
1100
1300
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FEDL63193-04
Semiconductor 1
ML63193
DC Characteristics (5)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = -20 to +70C unless otherwise specified) Parameter Symbol Condition VDDI = 1.5 V IOH1 VOH1 = VDDI - 0.5 V VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V IOL1 VOL1 = 0.5 V VDDI = 3.0 V VDDI = 5.0 V VDD = 1.5 V IOH2 Output Current 2 (MD, MDB) IOL2 IOH3 IOHM3 IOHM3S IOMH3 Output Current 3 (SEG0 to SEG63) (COM1 to COM16) IOMH3S IOML3 IOML3S IOLM3 IOLM3S IOL3 IOH4R IOL4R IOH4C IOL4C Output Leakage Current (P2.0 to P2.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) IOOL VOL = VSS -0.3 -- -- VOL2 = 0.7 V VOH2 = VDD - 0.7 V VDD = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V VDD = 3.0 V VDD = VDDH = 5.0 V VOH3 = VDD5 - 0.2 V (VDD5 level) VOHM3 = VDD4 + 0.2 V (VDD4 level) VOHM3S = VDD4 - 0.2 V (VDD4 level) VOMH3 = VDD3 + 0.2 V (VDD3 level) VOMH3S = VDD3 - 0.2 V (VDD3 level) VOML3 = VDD2 + 0.2 V (VDD2 level) VOML3S = VDD2 - 0.2 V (VDD2 level) VOLM3 = VDD1 + 0.2 V (VDD1 level) VOLM3S = VDD1 - 0.2 V (VDD1 level) VOL3 = VSS + 0.2 V (VSS level) VOH4R = VDDH - 0.5 V (RC oscillation) VOL4R = 0.5 V (RC oscillation) VOH4C = VDDH - 0.5 V (ceramic oscillation) VOL4c = 0.5 V (ceramic oscillation) VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V Min. -2.5 -6.0 -8.5 0.4 1.0 1.5 -4.0 -11.0 -14.0 0.5 2.0 4.0 - 4 -- 4 -- 4 -- 4 -- 4 -2.5 -3.5 0.25 0.5 -500 -800 200 400 Typ. -1.4 -3.5 -5.0 1.4 3.0 3.7 -2.0 -6.0 -9.0 2.0 5.5 7.0 -- -- -- -- -- -- -- -- -- -- -1.3 -1.7 1.5 1.8 -250 -350 500 700 Max. -0.4 -1.0 -1.5 2.5 6.0 8.5 -0.5 -2.0 -4.0 4.0 11.0 14.0 -4 -- -4 -- -4 -- -4 -- -4 -- -0.25 -0.5 2.5 3.5 -100 -200 800 1000 A mA A 2 mA Unit Measuring Circuit
Output Current 1 (P9.0 to P9.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3)
Output Current 4 (OSC1)
IOOH
VOH = VDDI
--
--
0.3
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FEDL63193-04
Semiconductor 1
ML63193
DC Characteristics (6)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = -20 to +70C unless otherwise specified) Parameter Symbol Condition VDDI = 1.5 V VDDI = 3.0 V VDDI = 5.0 V IIL1 VIL1 = VSS (when pulled up) VDDI = 1.5 V VDDI = 3.0 V VDDI = 5.0 V IIH1Z IIL1Z IIL2 IIH2R Input Current 2 (OSC0) IIL2R IIH2C VIH1 = VDDI (in a high impedance state) VIL1 = VSS (in a high impedance state) VIL2 = VSS (when pulled up) VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V Min. 2 30 70 -45 -260 -650 0 -1 -350 -750 0 -1 0.5 3 -4.0 -10 10 150 0.5 -1 VDD = 1.5 V Input Current 4 (TST1, TST2) IIH4 IIL4 VIH4 = VDD VIL4 = VSS VDD = 3.0 V VDD = VDDH = 5.0 V 50 0.5 2.0 -1 Typ. 20 120 350 -20 -120 -350 -- -- -170 -450 -- -- 1.8 6 -1.8 -6 180 1100 2.7 -- 750 3.0 6.5 -- Max. 45 260 650 -2 -30 -70 1 0 -30 -200 1 0 4.0 10 -0.5 -3 350 2400 5.0 0 1500 5.5 11.0 0 mA A mA A 3 A Unit Measuring Circuit
IIH1 Input Current 1 (P0.0 to P0.3) (P9.0 to P9.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3)
VIH1 = VDDI (when pulled down)
VIH2R = VDDH (RC oscillation) VIL2R = VSS (RC oscillation) VIH2C = VDDH (ceramic oscillation) VIL2C = VSS (ceramic oscillation) VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V VDD = 3.0 V VDD = VDDH = 5.0 V VIL3 = VSS
IIL2C
Input Current 3 (RESET)
IIH3 IIL3
VIH3 = VDD
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FEDL63193-04
Semiconductor 1
ML63193
DC Characteristics (7)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = -20 to +70C unless otherwise specified) Parameter Input Voltage 1 (P0.0 to P0.3) (P9.0 to P9.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) Input Voltage 2 (OSC0) Symbol Condition VDDI = 1.5 V VIH1 VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V VIL1 VDDI = 3.0 V VDDI = 5.0 V VIH2 VIL2 Input Voltage 3 (RESET), (TST1), (TST2) VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V VIH3 VDD = 3.0 V VDD = 5.0 V VDD = 1.5 V VIL3 Hysteresis Width 1 (P0.0 to P0.3) (P9.0 to P9.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) Hysteresis Width 2 (RESET), (TST1), (TST2) Input Pin Capacitance (P0.0 to P0.3) (P9.0 to P9.3) (PA.0 to PA.3) (PB.0 to PB.3) (PC.0 to PC.3) (PE.0 to PE.3) VT2 VDD = 3.0 V VDD = 5.0 V VDDI = 1.5 V VT1 VDDI = 3.0 V VDDI = 5.0 V VDD = 1.5 V VDD = 3.0 V VDD = 5.0 V Min. 1.2 2.4 4.0 0 0 0 2.4 4.0 0 0 1.35 2.4 4.0 0 0 0 0.05 0.2 0.25 0.05 0.2 0.25 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 0.5 1.0 0.1 0.5 1.0 Max. 1.5 3.0 5.0 0.3 0.6 1 3.0 5.0 0.6 1 1.5 3.0 5.0 0.15 0.6 1 0.3 1.0 1.5 0.3 1.0 1.5 V 4 Unit Measuring Circuit
CIN
--
--
--
5
pF
1
28/37
FEDL63193-04
Semiconductor 1
ML63193
Measuring circuit 1 CB1 Cb12 CB2 C1 C12 1 2 C2 OSC0 OSC1 VSS VDD A VDDI VDD1 Ca V VDD2 Cb V : : : : : : VDD3 Cc V VDD4 Cd V VDD5 Ce V VDDH Ch V VDDL Cl V XT0 XT1 3 *2 4
*1
Ca, Cb, Cc, Cd, Ce, Cl, C12 Ch, Cb12 CG CL0 CL1 Ceramic Resonator
0.1 F 1 F 15 pF 30 pF 30 pF CSA2.00MG (2 MHz) CSB1000J (1 MHz) (Murata MFG.-make) *2 RC Oscillator
*1 RC Oscillator 1 ROSH 2 Ceramic Oscillator CL0
3 ROSL 4 Crystal Oscillator CG 3 Crystal 4
1 Ceramic Resonator 2
CL1
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FEDL63193-04
Semiconductor 1
ML63193
Measuring circuit 2
VIH
*4
*3
INPUT
OUTPUT
A
VIL
VSS
VDD
VDDI
VDD1
VDD2
VDD3
VDD4
VDD5
VDDH
VDDL
*3 Input logic circuit to determine the specified measuring conditions. *4 Measured at the specified output pins.
Measuring circuit 3
*5
A
INPUT
OUTPUT
VSS
VDD
VDDI
VDD1
VDD2
VDD3
VDD4
VDD5
VDDH
VDDL
Measuring circuit 4
VIH
*5
INPUT
OUTPUT
Waveform Monitoring
VIL
VSS
VDD
VDDI
VDD1
VDD2
VDD3
VDD4
VDD5
VDDH
VDDL
*5 Measured at the specified input pins.
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Semiconductor 1
ML63193
AC Characteristics (Serial Interface, Serial Port)
(1) Synchronous Communication (VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = -20 to +70C unless otherwise specified) Parameter TXC/RXC Input Fall Time TXC/RXC Input Rise Time TXC/RXC Input "L" Level Pulse Width TXC/RXC Input "H" Level Pulse Width TXC/RXC Input Cycle Time TXC/RXC Output Cycle Time TXD Output Delay Time RXD Input Setup Time RXD Input Hold Time Symbol tf tr tCWL tCWH tCYC tCYC (O) tDDR tDS tDH Condition -- -- -- -- -- CPU is in operating at 32.768 kHz Output load capacitance 10 pF -- -- Min. -- -- 0.8 0.8 2.0 -- -- 0.5 0.8 Typ. -- -- -- -- -- 30.5 -- -- -- Max. 1.0 1.0 -- -- -- -- 0.4 -- -- s Unit
Synchronous communication timing ("H" level = 4.0 V, "L" level = 1.0 V)
tCYC TXC (PC.1)/ RXC (PC.2) tr tCWH tDDR TXD (PC.3) VSS tDS RXD (PC.0) VSS tDH tDS VDDI tDDR VDDI tf tCWL VDDI VSS
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FEDL63193-04
Semiconductor 1
ML63193
(2) UART Communication Parameter Transmit Baud Rate Receive Baud Rate Symbol TBRT RBRT Condition TBRT = 1/fBRT TCR = 1/fOSC RBRT = 1/fBRT Min. TBRT - TCR RBRT x 0.97 Typ. TBRT RBRT Max. TBRT + TCR RBRT x 1.03 Unit s
fBRT: Baud rates (1200, 2400, 4800, 9600 bps)
UART communication timing ("H" level = 4.0 V, "L" level = 1.0 V)
TBRT TXD (PC.3) RBRT VDDI RXD (PC.0) VSS VDDI VSS
32/37
FEDL63193-04
Semiconductor 1
ML63193
AC Characteristics (Serial Interface, Shift Register)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VDDI = 5.0 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified) Parameter SCLK Input Fall Time SCLK Input Rise Time SCLK Input "L" Level Pulse Width SCLK Input "H" Level Pulse Width SCLK Input Cycle Time Symbol tf tr tCWL tCWH tCYC tCYC1(O) SCLK Output Cycle Time tCYC2(O) SOUT Output Delay Time SIN Input Setup Time SIN Input Hold Time tDDR tDS tDH CPU is in operating at 32.768 kHz CPU is in operating at 2 MHz VDD = VDDH = 1.8 to 3.5 V CL = 10 pF -- -- Condition -- -- -- -- Min. -- -- 0.8 0.8 1.8 -- -- -- 0.5 0.8 Typ. -- -- -- -- -- 30.5 0.5 -- -- -- Max. 1.0 1.0 -- -- -- -- -- 0.4 -- -- s Unit
AC characteristics timing ("H" level = 4.0 V, "L" level = 1.0 V)
tCYC VDDI SCLK (PE.2) VSS tr tCWH tDDR SOUT (PE.1) VSS tDS SIN (PE.0) VSS tDH tDS VDDI tDDR VDDI tf tCWL
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FEDL63193-04
Semiconductor 1
ML63193
APPLICATION CIRCUITS
* Crystal oscillation is selected as low-speed oscillation by mask option. * RC oscillation is selected as high-speed oscillation by software. * Ports are powered from external memory power source. * CV is an IC power supply bypass capacitor. * Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12, Ch, and CG, are for reference only. OSC0 ROSH 5 to 25 pF 1.5 V Ch 1.0 F XT1 VDDH VDD Cv 1.0 F CB1 1.0 F Cb12 0.1 F CB2 Cl VDDL 0.1 F Ce VDD5 0.1 F Cd VDD4 0.1 F Cc VDD3 0.1 F Cb VDD2 0.1 F Ca VDD1 C1 C12 0.1 F Push SW C2 RESET TST1 TST2 MD MDB VSS PE.3 PE.2 PE.1 PE.0 PC.3 PC.2 PC.1 PC.0 PB.3 PB.2 PB.1 PB.0 OSC1
LCD
Crystal 32.768 kHz CG
COM1-16 XT0
SEG0-63
ML63193
PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P0.3 P0.2 P0.1 P0.0 VDDI
Buzzer
VDD
Note:
VDDI is the power supply pin for the input-output ports. Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with Power Supply Backup
34/37
FEDL63193-04
Semiconductor 1
ML63193
LCD
* Crystal oscillation is selected as low-speed oscillation by mask option. * Ceramic oscillation is selected as high-speed oscillation by software. * Ports, external memory, and IC share their power supply. * Cv is an IC power supply bypass capacitor. * Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG, CL0, and CL1 are for reference only. CL0 30 pF OSC0 OSC1 CL1 30 pF PE.3 PE.2 PE.1 PE.0 PC.3 PC.2 PC.1 PC.0 PB.3 PB.2 PB.1 PB.0 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P0.3 P0.2 P0.1 P0.0 VDDI Ceramic Resonator (Example: 1 MHz)
Crystal 32.768 kHz CG VDD 5.0 V 0.1 F Cv Cl Ce Cd Cc Cv Ca Open 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F Push SW
COM1-16 XT0 XT1 VDDH VDD CB1 CB2 VDDL VDD5 VDD4 VDD3 VDD2 VDD1 C1
SEG0-63
5 to 25 pF
ML63193
C12
C2 RESET TST1 TST2 MD MDB VSS
Buzzer
VDD
Note:
VDDI is the power supply pin for the input-output ports. Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with No Power Supply Backup
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FEDL63193-04
Semiconductor 1
ML63193
PACKAGE DIMENSIONS
(Unit : mm)
LQFP144-P-2020-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.37 TYP. 5/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL63193-04
Semiconductor 1
ML63193
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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